A next-generation electronic product is asked to have multiple functions and high-speed performance other than compactness. The integrated-circuit manufacturers have moved to smaller design rules to make chips with much more electronic devices. On the other hand, the techniques for packaging the chips or semiconductor substrates have also been developed for the same purpose.
Conventionally, the molding compound layer in a package substrate is formed by using transfer molding or injection molding. For example, FIGS. 1A to 1C show cross-sectional views of a package substrate in different steps of a prior-art fabrication process. The package substrate has a wiring layer 12 and metal pillars 13 on a carrier 11, as shown in FIG. 1A. Before the formation of molding compound layers 14 on the wiring layer 12 and the metal pillars 13, the top surface of the carrier 11 is divided into grid regions. The molding compound layers 14 are formed in turn by molding and each of the molding compound layers 14 is located in a grid region. A molding compound layer 14 can be formed on the wiring layer 12 and the metal pillars 13 in the left region of the carrier 11 as shown in FIG. 1B. Then another molding compound layer 14 can be formed on the wiring layer 12 and the metal pillars 13 in the right region of the carrier 11 as shown in FIG. 1C. Thus, gaps or recesses may be formed between the neighboring molding compound layers 14 and they may introduce chemical contamination caused by the dielectric processing in the subsequent fabrication process and the possible baring of the carrier 11. And the multiple-step molding process may require more processing time. Therefore, it is in need to develop a new means for fabricating package substrates.